Large scale integrated circuit (LSI) devices represented by semiconductor integrated circuits have steadily been developed in performance over 30 years since their invention mainly through device microfabrication. Nowadays, however, various physical limits manifest themselves in device microfabrication and it is becoming extremely difficult to produce integrated circuit devices which are stable and uniform in quality. Depending only on device microfabrication is approaching its limit in enhancing LSI devices in performance. Conventional LSI designing technology based on fabrication of uniform devices should be reviewed.
Furthermore, as device microfabrication has further been pursued, recent LSI devices are further increased in size and increasingly highly integrated and a system is now implemented on-chip, and it is now essential that a large number of various functional circuits be integrated internal to a chip. In designing such a large-scale LSI device, it is particularly important to optimally adjust for example a timing of operation between the large number of integrated functional circuits to accurately operate the circuits. However, as LSIs have further various and complicated functions integrated therein, ensuring an operating margin for covering a process variation unavoidable in the LSI's production process has become an obstacle to further enhancing a large-scale LSI device in performance in future. In other words, enhancing the LSI device in performance in future essentially entails a development of a new LSI design and production means accommodating a variation in device characteristics that is large to an extent.
Such an issue as no longer ignorable in enhancing an LSI device in performance that is associated with unevenness of devices that varies for each LSI chip produced, such as a spatial variation in device characteristics in a chip and a variation of a median of device characteristics that is attributed to a process variation, can effectively be addressed by providing the exact LSI chip with a so-called self-adaptive or optimizing function, a function to automatically adjust and compensate for a variation in characteristics of integrated devices for each LSI chip to enhance device performance.
However, this has not readily been implemented with conventional technology. Conventionally, using a plurality of MOS transistors and for example switching the number of their parallel connections via an electrical switch, as implemented in a circuit, was a possible means for mounting a self adjustment function on an LSI chip. This technique, however, is significantly inefficient in terms of precision in adjustment, and circuit scale.
FIGS. 12 to 15A and 15B show an exemplary configuration of a circuit capable of electrically modulating a substantial gain coefficient of an MOS transistor by using a plurality of MOS transistors. FIG. 12 shows an exemplary configuration of a circuit with two MOS transistors 11 and 12 connected in parallel. Transistor 11 has a gate electrode receiving a normal signal voltage and transistor 12 has gate electrode receiving a signal voltage or an OFF voltage (a voltage for which the MOS transistor turns off) depending on a switch 13. Switch 13 is typically configured by a CMOS switch (a parallel connection of p-MOS and n-MOS), a single inverter producing a gate signal thereof and a latch circuit for holding a state of the switch, and it requires a total of approximately 24 transistors. When switch 13 connects the gate electrode of transistor 12 to a signal voltage, this circuit operates as an MOS transistor with transistors 11 and 12 connected in parallel. When switch 13 connects the gate electrode of transistor 12 to the OFF voltage, in this circuit, only transistor 11 operates.
FIG. 13 shows an exemplary configuration of a circuit with five transistors connected in parallel. There can be implemented 16 variations depending on states of four switches 13. Setting each of gain coefficients of four transistors 12 raised to a power of 2 can provide a coefficient having a value in 16 levels at equal intervals.
FIG. 14A shows an exemplary configuration of a circuit with two MOS transistors connected in series. In this example, switch 13 connects the gate electrode of transistor 12 to either a signal voltage or an ON voltage (a voltage for which the MOS transistor turns on). As shown in FIG. 14B, when switch 13 connects the gate electrode of transistor 12 to the signal voltage, the circuit operates as an MOS transistor with transistors 11 and 12 connected in series. In contrast, as shown in FIG. 140, when switch 13 connects the gate electrode of transistor 12 to the ON voltage, the circuit operates as a circuit with the transistor 12 ON resistance connected to transistor 11 in series.
FIG. 15A shows an example of a configuration applying a control voltage to the gate electrode of transistor 12 and depending on the control voltage value to adjust a resistance connected to transistor 11 in series. More specifically, as shown in FIG. 15B, transistor 12 serves as a variable resistance having a value in resistance corresponding to the control voltage.
The FIGS. 12 and 13 circuit configuration examples based on parallel connection are disadvantageous as precision with which characteristics can be adjusted and circuit scale have a trade-off relationship and enhanced precision of adjustment results in an increased circuit scale. Furthermore, the FIGS. 14A–14C and 15A–15B circuit configuration examples based on series connection disadvantageously result in increased circuit scales and in addition provide an effective range of adjustment of characteristics that is limited by series interposition of a component of resistance indicating non-linear characteristics relative to an input signal.
A system modulating electrical characteristics of a transistor that depends on such a circuit configuration as described above has inherently imposed thereon a restriction that a number of devices several to several ten times that of devices to be adjusted needs to be consumed. As such, it hardly conforms with mounting a self-adjustment function for the purpose of pursuing high integration and enhancing the LSI in performance. Accordingly there is a demand for development of a new semiconductor device allowing high-precision modulation of electrical characteristics without interfering with high integration.